1. Field of the Invention
This invention relates to digital systems and microprocessors, and more particularly to multiplexed address/data bus schemes for digital systems that minimize pin count.
2. Description of the Relevant Art
Microprocessors have wide spread applications in the electronics industry. Manufacturers have reduced the cost of microprocessors by providing low-cost packaging, and one way of providing low-cost packaging is by reducing the number of pins needed to connect the microprocessor to external circuitry.
One commonly known method of reducing pin count involves the use of time multiplexed address and data buses. In such a bus scheme, the same set of pins is used to carry address information in one phase of the transaction, and data information in another phase. Typically, an electrical component such as a microprocessor which uses such a bus structure also includes a control signal, ALE, to allow the bus to be demultiplexed externally.
However, for a number of reasons, more than just the address of the transfer is needed when performing a bus operation. In the least, the size of the transfer must be provided; for example, to differentiate between writing a byte, halfword, or fullword at a given address.
There are a number of traditional approaches to this problem. One approach is to encode the size of the transfer on dedicated pins and let external logic decode the bytes of the bus which are involved in the transfer. The other method is to have the processor decode the size of the transfer and provide dedicated byte strobes. The advantage to this approach is that these strobes can be directly used in the memory control system without external logic as required in the other approach. The disadvantage of this approach is that four pins are required for the byte strobes.
An additional complication may occur with microprocessors if it is desired to process certain types of reads of a plurality of adjacent words. For example, it may be desirable to read four adjacent four byte words. For many microprocessors, the order of the words in such quad reads is always the same; for example, word 0 of the block followed by word 1 followed by word 2 and ending with word 3.
When this type of read occurs, the memory system must respond with the appropriate four words in the correct order. Thus, the word within block address lines at the memory must function as counter. When this is done externally with an external counter, additional chips are required. Moreover, if this is done on a typical multiplexed bus, a net loss of performance occurs since a block read required four addressing phases for four data phases.
Although multiplexed buses have been available in previous microprocessors, such microprocessors do not include a burst address counter or byte enables. It is desirable for cost and performance to provide a minimum pin count multiplexed address/data bus microprocessor system with byte enable and burst address counter support.